1. Field of the Invention
The present invention relates to a test apparatus and an electronic device. More particularly, the present invention relates to a test apparatus that tests a device under test and an electronic device including a test circuit that tests a circuit under test.
2. Related Art
A test apparatus for testing a device under test such as a semiconductor has been known. The test apparatus supplies a test signal with a predetermined logical pattern to the device under test, and detects a signal output from the device under test in accordance with this test signal. Then, the test apparatus compares the detected signal and an expected value to decide the good or bad of the device under test.
The test apparatus includes a main memory such as DRAM that stores sequence data (a test instruction stream) determining a test sequence for testing the device under test, a cache memory that temporarily stores a test instruction stream, a pattern generator that sequentially generates a test pattern, and a test signal output section that outputs a test signal with logic according to the test pattern. The pattern generator sequentially reads instructions from the sequence data stored on the cache memory, and executes the read instructions. Then, the pattern generator reads pattern data corresponding to the executed instructions from the memory, and sequentially outputs the read pattern data as test patterns. According to this, the test apparatus can supply a test signal with a predetermined logical pattern to the device under test.
Moreover, the main memory can store a plurality of sequence data. In this case, the pattern generator selects one-by-one data out of the plurality of sequence data stored on the main memory in accordance with a list by which execution order of sequence data is determined, and sequentially executes them.
Here, the pattern generator can set a repeated interval on the list by which execution order is determined, in order to repeatedly execute the predetermined number of sequence data (Japanese Patent Application Publication No. 1996-094724). However, since execution order is prescribed in sequence data unit on the list, it was difficult to set a repeated interval so that the pattern generator starts from a halfway instruction of sequence data and ends at a halfway instruction of the other sequence data.
Moreover, the pattern generator can insert a branch instruction into sequence data to repeatedly execute an instruction stream. However, since an instruction stream is closed every sequence data even if the branch instruction is inserted, a process cannot be moved to the other sequence data. Therefore, it was difficult to set a repeated interval so that the pattern generator starts from a halfway instruction of sequence data and ends at a halfway instruction of the other sequence data.